How the computer fits together.

I started with an 8-bit ALU containing 3,488 transistors in total: 624 discrete MOSFETs and 2,864 inside 74HC logic chips. Tomato takes that work into a programmable, 32-bit computer. Its Dual-LUT ALU combines two Boolean functions and carry in one arithmetic operation.

The instruction word, ALU, and register operands are 32 bits wide. Instruction overlays, the immediate box, and the Dual-LUT let me explore how operations map onto the same datapath. The ISA profiles are exploration data: mnemonic and operation comparisons, not implemented decoders, tested foreign binaries, or evidence of native compatibility. Expanding and testing Tomato instruction coverage is part of my software work.

The dual-LUT slice is the center. Matching every LUT pair to its own instruction was never the goal. The 512-row ROM burns what programs need today; the rest of the plane waits in the LUT catalog until a program asks.

Fetch to write-back

The following is the conceptual path shared by the implementations:

The program counter fetches from memory into the IR. The register file presents three read ports and accepts one write. ALU control, memory I/O, memory bus, and PC each have their own decode EEPROM—small boards sitting next to the hardware they drive, all listening to the same opcode from the IR. The dual-LUT ALU result returns through the write-back mux on lot 06, not through a cascading 151 tree that would cost tens of nanoseconds per hop.

There is no single linear authority chain. Use the evidence that governs the question: hand-written FPGA RTL for the running FPGA machine; KiCad files, fabrication records, and assembly evidence for physical boards; the burned ROM and ISA tables for instruction encoding; assembler and OS sources for software behavior; and dated journal entries only for what was proposed or observed at that date. Digital schematics are editable design exploration, while exported Verilog is read-only sign-off for that schematic flow.

Dual-LUT slice

alu_out = adder( f(a, b, c), g(a, b, c), carry_in )

The nibble sliceLUT3 feeds the adder directly. No arithmetic/logic mode mux at the output.

Per nibble, two independent 3-input LUT planes—each a 74ACT151 programmed by an 8-bit opcode bus—sum through a ripple adder. The old topology raced arithmetic and logic into eight 74257 mode muxes at the end of the slice; that branch is gone (why the muxes left). LUT output feeds the adder directly. Carry select uses 74251 muxes; carry-bypass lives inside the 4-bit cell. Every chip gets a 0.1 µF decoupling cap beside it. Toggle the slice in the playground while the first board fills.

Verification ladder: alu-1b-final → 2× alu-4b → 4× alu-8b → alu-32b-final. Lot 07_alu implements one 8-bit slice in copper—99.95×99.80 mm, 25 logic ICs per 8b, soldered and on the bench. Lot 01_alu is the 3,488-transistor predecessor—complete on paper, set aside. The Dual-LUT playground is still the same slice: toggle A, B, C, both opcodes, and carry, then resolve a program from the output you want. Assembly dispatch

The word

Typical packing for ALU register ops. Low bits are often double-booked as immediate or branch overlay, depending on the mnemonic.

Native ALU syntax, conceptual: opcode rd, rA, rB, rC — destination is f + g + cin. The architectural register file is 32,768 × 32-bit — that is the primary count, because discrete is the superior design constraint. Thirty-two names times eight banks is the FPGA stand-in: 256 × 32-bit locations, with r0 hardwired to zero, because there is no space for more on that fabric. The current burned ISA addresses that 256-entry array. Low bits double-book as branch condition, jump mode, or immediate overlay depending on the mnemonic—the same slices, different assembly spellings. Field layout authority: opcode-map.csv.

Modular decode

One central microcode blob is elegant in simulation and miserable on a breadboard: twenty-something control wires crawling to the wrong places. Tomato split decode into small boards with local EEPROMs. They all listen to the same opcode from the IR; each sits next to the hardware it drives.

• ALU control — opcode, operand prep, carry select. Lives on the ALU board.
• Shift / mul-div control — shift mode, multiply enable, priority-encoder mux.
• IR / register / writeback — immediate encoding, writeback source, register write.
• Memory I/O — bank, read/write, byte lane. Flag-write comes out here too.
• Memory bus — what is on the address bus, how store data is picked.
• PC / stack — branches, jumps, link, conditions. Two small ROMs where fields would not pack.

HALT stays on main—opcode plus execute phase, one comparator, not worth its own board. Short ribbons; bring-up in pieces. The master catalog stays the source of truth; a script cuts per-board images. The cost is several EEPROMs instead of one, and opcode fanout to all of them. See the modularization journal for the wiring problem that forced the split.

The full datapathDigital schematic: local control boards and the data paths they drive.