Lot 04 · Register · In design

256 names, three reads, one write — the monstrous GPR file.

This unbuilt discrete board is the 32,768-location, 3-read-1-write SRAM file — the primary architectural count. FPGA RTL stays at 256 × 32-bit registers in eight banks, with r0 hardwired to zero, because there is no space for more. The instruction register sheet is part of the same board.

KiCad · 04_register · Why 32,768?

The 32-bit instruction word carries five register fields—rd, rA, rB, rC, and a 3-bit bank—so the physical file must serve three concurrent read ports and one write port without turning the PCB into a fire hazard. Digital already models the behaviour; the board work is fanout, tri-state discipline, and decode EEPROMs sitting next to the storage arrays.

Sheets

register.kicad_sch — GPR arrays and read/write port muxing. ir.kicad_sch — instruction register latch and hold timing relative to fetch. Decode stays local: universal 10-bit opcode into combinational EEPROM, same pattern as every other slice in the stack.

GPRs: 256 · 3R1W
Banks: 8 · via 3-bit bank field
Status: In design · schematic started
Project: hardware/kicad/boards/04_register/