tomatoDispatch · General Purpose Register File
A historical proposal to grow a discrete SRAM register file from 32 to 32,768 locations. Current FPGA RTL uses 256 × 32-bit registers.
Note
This proposal would expose 32,768 32-bit GPR locations because the selected discrete SRAMs (AS6C62256-55PCN, 32K × 8) provide a full 15-bit address space. It describes a proposed mirrored 3R1W discrete structure, not the current FPGA register file.
That is 128 KiB of logical register storage. The comparison with half a Blackwell SM concerns capacity only; it does not compare access behavior or performance.
How the file grew
[ superbank:7 ][ bank:3 ][ register:5 ]
7 + 3 + 5 = 15 → 32,768 × 32-bit locations
Historical warning — current context (16 September 2026): this entry records a 32,768-location discrete-memory proposal. Current FPGA RTL implements 256 × 32-bit registers in eight banks, with r0 hardwired to zero. SETBANK2 and the seven-bit superbank are not present in that RTL.
It was only right to start Tomato with the conventional 32 general-purpose registers. But there was an obvious waste: the discrete register file was already going to use parallel asynchronous SRAMs with thousands of available addresses.
The 7-bit secondary bank is not carried inside every ordinary instruction. It is architectural state. A dedicated custom op changes it:
SETBANK2 0x03 → superbank_latch ← 0x03
physical_address = { superbank_latch, bank, register }
One operation changes the entire visible 256-register window — no copying, no spill to RAM, no widening normal instructions. Ordinary encoding stays:
[ opcode:9 ][ D:5 ][ A:5 ][ B:5 ][ C:5 ][ overlay:3 ]
while the upper seven address bits live in the latch until the next SETBANK2.
Tomato's ALU needs three independent register operands, so the file needs three reads and one write. Ordinary async SRAM does not provide that, so the file is mirrored three times.
Four ×8 SRAMs make one 32-bit mirror (4 × (32K × 8) = 32K × 32). Three identical mirrors give the three read ports:
Broadcast write
One address + data fan out to every mirror · 1W
4 × (32K × 8) per mirror · 12 AS6C62256 total · effective 3R1W
Writes broadcast address and data to all three; reads present independent addresses. Effective 3R1W from 12 ordinary SRAM chips — no exotic multiported part.
On an 8K-deep device, 32 architectural registers used 0.39% of the address depth. Tomato's existing 3-bit bank field grew that to 256 GPR — still only 3.125%. The SRAMs, PCB area, 32-bit buses, and three mirrors were already paid for. The unused depth was just sitting there.
Part comparison · same 55 ns class · same 12-chip 3R1W
| AS6C6264 | AS6C62256-55PCN | |
|---|---|---|
| Organization | 8K × 8 | 32K × 8 |
| Capacity | 64 Kbit | 256 Kbit |
| Address bits | 13 | 15 |
| 32-bit addresses per mirror | 8,192 | 32,768 |
| Access time | 55 ns | 55 ns |
| Supply | 2.7–5.5 V | 2.7–5.5 V |
| Interface | Async parallel | Async parallel |
| Chips needed for 3R1W | 12 | 12 |
| Approx. 12-chip cost* | ~USD 114 | ~USD 122 |
*Pricing observed during this comparison; distributor and quantity pricing will move.
For roughly USD 7 more across the whole register file: 4× the depth, same chip count, same 55 ns class. So instead of leaving two address lines unused, expose the full device:
128 superbanks × 8 primary banks × 32 registers = 32,768 GPR
And yes — that number is absurd.
Integer register space · selected architectures
| Architecture | Integer / register space |
|---|---|
| x86-64 | 16 |
| ARM AArch64 | 31 |
| RISC-V RV32I | 32 |
| NVIDIA Blackwell | 255 / thread · 65,536 / SM |
| Tomato | 256 / instruction · 32,768 |
Tomato vs the baselines
| Baseline | Register space | vs Tomato |
|---|---|---|
| x86-64 | 16 GPR | 2,048× |
| RISC-V RV32I | 32 GPR | 1,024× |
| NVIDIA Blackwell SM | 65,536 × 32-bit physical | ½ (half) |
| Tomato | 256 per instruction · 32,768 in the file | — |
The AS6C62256 presents fifteen address bits; once twelve of those chips are in the BOM for 3R1W, wiring them fully is the only move that isn't waste.
A flat 32K-register ISA would still be terrible: fifteen bits per operand × four → 60 bits just naming registers. Banking keeps the common 5-bit fields and amortizes the upper bits:
SETBANK2 0x57 ADD r4, r7, r12 MUL r2, r9, r20 …
All of those ops stay inside the window selected by 0x57 until another bank op changes it. Huge file; ordinary instruction width unchanged.
Superbank latch
superbank:7
15-bit SRAM address
1 of 32,768 GPR
Port map
256 per instruction window · SETBANK2 moves the superbank field
This proposal started as an attempt not to waste SRAM address pins. It would have exposed 32,768 GPR; current FPGA Tomato instead has 256 × 32-bit registers.
From the build
Datapath and control connected in Digital.
The menu running through the FPGA display path.