Lot 03 · Memory · In design
Dual-port RAM and the tile framebuffer — the bus to the outside.
True dual-port RAM, byte-lane decode, and a fixed 60×80 tile framebuffer—the same graphics-block philosophy as the predecessor board, now on the 32-bit highway.
Memory is where Tomato stops being “just an ALU demo” and becomes a machine you can program against. The board hosts RAM interfaces, byte-lane decoding for unaligned access, and the custom graphics block anchored bottom-left on the layout—identical instinct to 01_alu, scaled to a 32-bit word. During FPGA verification the polling path becomes a proper Video Processing Unit (VPU); on copper it is ribbons, headers, and careful bus timing.
Sheets in KiCad
03_memory.kicad_sch — top-level memory and load/store plumbing. byte-lane-decoder.kicad_sch — which bytes participate on a 32-bit transaction. vga.kicad_sch — timing and tile scan for the 60×80 surface. Everything listens to the same IR opcode via local EEPROM decode on the finished board stack.
- Framebuffer
- 60 × 80 tiles · fixed map
- RAM
- Dual-port · eBay score on bench list
- Status
- In design · schematic started
- Project
hardware/kicad/boards/03_memory/
Related journal: Load/store · Display dispatch.