tomatoTomato / Build & evidence
I designed a custom 32-bit computer, implemented it on FPGA, and wrote the software it runs. Now I’m turning that architecture into a complete discrete machine, board by board.
Tyrone Marhguy · Penn Computer Engineering · Independent project
01 / Running on FPGA
The complete Nexys A7 FPGA computer boots the assembly-written Tomato OS v3.0 with fourteen menu entries, including Envelop, games, and system tools. The default CPU clock is 6.25 MHz; 90 MHz is only the nextpnr timing target.
The running-machine recordThe custom 32-bit ALU computes two independently programmed functions of A, B, and C, then adds them with carry: f(A,B,C) + g(A,B,C) + carry.
Inspect the datapathInstruction tables and the assembler connect the architecture to executable software. The software stack is part of the machine I built.
Explore the software02 / Messaging with Envelop
Envelop firmware, setup data, and a bounded remote executor are linked into Tomato OS v3.0. Web/native clients, backend, and bridge software are available in the separate Envelop project.
Follow the message pathA programmed FPGA, attached radio, current authenticated bridge lease, and completed Physical Tomato reply require live evidence. Available bridge software alone is not “online.”
The functional browser emulator runs the generated OS image at ISA level. It is not RTL, FPGA, or the discrete ALU board, and its results remain explicitly labeled.
Play the virtual machine03 / Physical hardware
Lot 07 is the fabricated and soldered 8-bit discrete slice of Tomato’s Dual-LUT ALU. Its bench hardware is real; it is not a complete discrete CPU.
See it on the homepageRegister, memory, control, and peripheral board work continues. The complete discrete CPU is the build in progress; the FPGA computer is already running.
Follow the board catalog04 / Simulation & formal verification
The verification record reports a 130-billion-vector 32-bit ALU Verilator run checked against a reference model. The reproducible harness is checked in; the full run log is not.
Methods and reproduction commandsThe counter FSM searches every LUT pair for fixed A, B, C, carry, and expected-output values. A hit verifies that one example, not a complete truth table or general function.
Inspect the compilerFormal checks cover the stated ALU properties at 1, 8, and 32 bits. Their assumptions and scope are part of the evidence.
Inspect the sign-off flowVerilog simulation and software running on FPGA exercise the complete computer. Whole-CPU formal verification remains future work.
Read the verification FAQ05 / Next in the build
Finish and connect the remaining boards, then test their timing and behavior together.
Grow the applications and instruction coverage that put the configurable ALU to work.
Pre-adder and post-adder shifting remain experiments. An LLVM backend is a future direction, not a finished deliverable.
The open design questionsAn invitation to engineers
I’m interested in detailed criticism of the Dual-LUT datapath, the verification assumptions, and the transition from FPGA to discrete hardware. A counterexample, a reproduced result, or a better timing argument can shape the next version.