From circuit boards to a running OS.

The current generated OS image runs the Envelop client inside the browser CPU emulator. This is virtual execution with simulated peripherals; it does not prove a programmed FPGA, radio session, or online bridge. Follow the complete message journey.

Envelop rendered through the FPGA display path. The frame records the interface and reported bridge state at capture time; it is not evidence that a bridge is currently online.

The FPGA display path shows Envelop returning a bounded compute result. The frame records the interface and reported bridge state at capture time; it does not establish that a bridge is currently online.

Desktop, menu, and games on the FPGA computer—clean HDMI capture, not a phone pointed at a monitor. Same clip featured on the Tomato OS page.

Iron on the desk. Boards and DigiKey parts were already ordered — just waiting on delivery.

TomatoOS desktop home—wallpaper on the FPGA path. The rest of the computer catching up to the ALU.

A historical twelve-entry menu capture; Tomato OS v3.0 now has fourteen entries, including Envelop and Compiler, off one jump table. Same screen as the menu sheet.

What Tomato is, in its own words — Dual-LUT ALU, register file, immediate box, and all, straight off the HDMI stream.

Thirty cells in, gold clues fixed. Same screen as the OS sheet.

MASKADD in one ALU pass against the two-instruction RV32I reference — match checked on the CPU itself. Counts exclude loads and UI.

Sudoku without waiting on the full keyboard matrix. Move with arrows; cycle 1–9 with another button.

Of course Tomato needs Sudoku—the paper book is always within arm’s reach.

Same desk, same habit—then the machine gets its own board.

Clean capture of Tomato OS from the HDMI stream—no filming the monitor.

The order that turns “can it produce video?” into “how do I capture it nicely?”

The main menu running live on the TV via the 12-bit PMOD. Six entries, all navigable with the D-pad.

Beyond Vivado. Yosys, nextpnr, and Project X-Ray compile the Tomato core to a bitstream on the Mac — terminal capture from synthesis through DONE. Same clip as the dispatch.

The slice under test. Copper on the mat, tools around it — the board is no longer a render.

Soldering lights on the loop, cut with the on-board test still every three seconds — desk, iron, then the slice on the mat.

The silicon on the copper at last. I got every mux down on one board, both adders, and the first few lamps of the debug wall. Holding it right next to the sim, the slice finally started looking like the machine I designed.

Tweezers, an iron, one SOIC at a time. Real parts on real pads instead of schematic symbols.

These indicators are insanely tiny. Align, don’t bridge it, repeat. I only managed to get seven on the wall at this point.

Five boards showed up. Continuity on power was clean on all of them. I still remember placing every trace on this outline.

And then the soldering began.

A slow pass over the stack. You can really see the mask colour, the edge plating, and that massive LED wall footprint right before I started populating them.

The most important screen on the system. Overcoming the low memory wall allowed this massive text block to be rendered by pulling from higher memory via pointers.

The very first bring-up step: checking continuity on VCC and GND across every board. They were perfectly clean on all five. No open pours, and definitely no shorted islands from the fab.

Soldered the PMOD pins, plugged in HDMI, got color bars — red, green, blue, gray. First sign the video path works.

The bring-up rig: Nexys A7 with the iCEBreaker 12-bit DVI PMOD seated on JC and JD, HDMI out, DONE lit after an open-source bitstream flash.

The same open toolchain ethic as the FPGA pivot on the Mac. LibreLane is where tapeout habits get tested before they touch Tomato copper.

Researching the FOSS FPGA and ASIC stacks that could replace slow closed tools. OpenROAD sits in the same toolbox as the Nexys bring-up Makefile.

After the VGA adapter refused to play along, I had to pivot. The PMOD order receipt from Mouser marks that shift in strategy.

The rest of the Mouser order. A CPU without a display is a heater, so this PMOD was critical to getting pixels on the screen.

DigiKey receipt for the 74xx parts. Drawing them is free. Buying them is not.

Checkout on JLC. Then you wait for the boards to show up.

The screen that used to flash for one frame before the debounce arithmetic fix. Now it reliably waits for the next key press.

Order placed. ENIG boards inbound.

Order summary. These line items become physical boards a week later.

Five boards for under six dollars. That was cheap enough to spin again without thinking twice if the fab made a mistake.

The delayed order. I got it replaced on the phone, and it finally showed up. After weeks of staring at schematics, the chips were finally a box I could actually hold.

That same sweep, but running on hardware. This FPGA clip confirmed the sim hit way before any copper was populated.

A brute-force sweep running in Digital. The AND3 family surfaces right at opcode 0x80, just before I replayed that exact same vector on real silicon.

The front-page orbit. I set up paper-stock lighting on the real mask colour. It's the exact same model you see on the interactive bench.

One of the first games on TomatoOS. Tetris on hardware you soldered hits different from an emulator.

The status bar at lock-in: every net closed, DRC passed, ready for Gerber export and JLCPCB.

July render with the green solder mask. The dual-LUT plane reads clearly in 3D long before any SOIC landed on the desk.

The back side: ground pours, stitching vias, and the underside of the LED wall. Two-layer boards still have a face you rarely show off.

The KiCad 3D render right before fab. Two alu_4b nibble cells chained on CIN-MAIN, complete with the flag block and an opcode lamp wall for bench debug.

The green check before checkout. No clearance violations, no unrouted nets — the board was allowed to leave the editor.

Nine footprints placed and a cloud of cyan airwires. This is the moment the schematic stops being abstract and starts demanding vias.

The schematic tree directly mirrors the Digital simulation. The hierarchy on the sheet matches the verification ladder exactly, right from 1b up through 8b.

The routed board before export. Two 4-bit cells, flag block, and the LED wall footprint all locked on one 100 mm square.

Racer on TomatoOS. Simple graphics; still fun because it is on the real machine.

The olive finish with Penn on the silk. Same geometry as the fab order — just the branding pass I wanted on the first spin.

The root sheet: power, connectors, and the two alu_4b instances that become the 8-bit slice.

One nibble cell: dual-LUT muxes, carry chain, and the opcode select that repeats across the word.

Zero, carry, negative, overflow — the flag block that turns arithmetic into branch conditions.

Bench headers and probe points. The slice has to be debuggable without a logic analyzer on every net.

The opcode lamp wall on its own sheet — one LED per function so the bench can read what the ALU is doing.

Decoders and support logic that tie the hierarchy together — the sheets you only notice when something does not enable.

The fab-ready top layer. 308 vias, 2404 segments, and I made sure every single net was closed before the order went out.

Feeding hex control into stacked 4-to-1s. This was the dual-LUT idea, still just a schematic and not yet 74ACT151 copper.

The Snake port game over screen. Built entirely with the parametric ISA and the new pseudo-instructions.

The heartbeat of the very early machine. I modeled the analog in Spice first, aiming for a square wave that the rest of the sim could actually trust.

The primitive here is just a mux. You land the opcode on the select pins, and the ALU bit becomes whatever the mux is wired to emit. Slice that cell and you get a word. Digital is where I tested that claim before locking in any footprint.

The same ISA, but absolutely no gates. I built this page to step the machine, mostly so the Digital netlist would have a referee to argue with.

The big sheet, running live. Just a program counter walking through a ROM I wrote.

Boxes before any footprints. Source A, Source B, destination, memory, and flags. Later sheets would test this exact unit in Digital. If the arrows lied, the sim was always going to say so louder than any DRC.

The living top sheet: control decode, alu-32b-final, register file, RAM and VGA, IR, PC, and the data-bus switch — labeled tomato-v1-burn. Same machine the FPGA and the OS boot from.

Mid-June: MMIO and arbiter experiments showing up on the same canvas as the ALU slices.

Late June — the sheet that became the front-page Digital plate. Custom programs and Fibonacci already behaving like a CPU.

Early June on the big sheet — still wiring the control spine before the custom programs ran clean.

Fibonacci on the slow clock — the usual sanity check once fetch and execute behave.

Another day on main.dig. The bus and register file start to look like a machine instead of a pile of parts.

Fetch and execute paths tightening. Each snapshot is a commit in the sim before any Gerber existed.

One memory, driving a lot of enables. Fanout is simply the tax you pay for having a centralized control unit.

A tiny state diagram that eventually grew into the full microcode.

Take the cell, lay it out eight times. This is the direct ancestor to the two 4-bit cells that eventually became 07_alu.

Shift implemented as a complete forest of 2-to-1s. This barrel shifter is exactly why the ALU does a lot more than just add.

The register is not empty. I ran a custom program that left a Fibonacci value sitting on Q and drove pin p. Seeing that number was the first time the paper machine actually behaved like a computer.

Memory-mapped I/O really only counts when the arbiter stops lying to you. It failed, then it passed, and then I captured this still.

Starting to convert an Amazon keyboard into a proper matrix. The 5 buttons on the A7 were too limiting for complex apps.

Microcode broken into modules instead of one unreadable sheet. Each block maps to a strobe the datapath can actually route.

The insight on the black card finally turned into a schematic that ran. The nibbles time-share a single ROM, and latches hold a digit each. Without doing this, every single hex lamp would have demanded its own decoder.

From hand-drawn hex patterns to a control sheet that drives segments from a nibble. The display problem stays a memory problem.

Ripple was honest, but lookahead was just faster. This wall of 74182s was the adder finally leaving the yellow pad.

Clock, counter, a couple EEPROMs, SRAM, a register file, eight 8-bit ALU blocks, and three hex walls. Microcode fans out the strobes, branch, halt, and the ALU function. 07_alu is really just one slice of this drawing, made small enough so I could actually fab it.

The nibble cell frozen in Digital before it became KiCad footprints. Two of these chained on CIN-MAIN became 07_alu.

Atlantic City. Another day, same project, just a different desk and different sand. The build logs caught all the odd offices.

October 2025. A full adder written out by hand. I found that efficiency is a sentence—the carry-out just reuses the XOR we already paid for in the sum. That ethic stuck.

Digits long before there was a ROM. I drew each nibble out as lamps by hand, just so a lookup table would actually have something to remember later.

The seven-segment display churning numbers live as Tomato runs.

Those same patterns, packed up for a chip. Once you have the glyphs, the display just turns into a memory problem.

Not every schematic was drawn under a lab light. Sometimes the keyboard sat on the beach, aimed at a grey horizon. The machine was portable way before it was ever a board.

The Nexys A7. Silicon that can pretend to be whatever netlist I throw at it. It sat there next to a PCB still routing—two different futures on the exact same desk.

The whole arithmetic unit laid out on one A2 sheet. Transceivers, SRAM, flag lamps, and all the connectors of the 32-bit machine I ended up walking away from.

Way too much machine for a first fab run. The traces do exist, but the board would have been the size of a poster.

The massive predecessor over on alu.tmarhguy.com. I used discrete MOSFETs there, whereas 07_alu packs dual-LUT logic cleanly into 74xx copper.

A 32-bit slice in KiCad with a ratsnest that was never going to become copper. 876 footprints and an ocean of cyan airwires. Walking away was a design decision. 07_alu is the board that actually fit a panel and a budget.

It was pretty enough to keep the render. Just not small enough to order five of.