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tomato

Instruction set

Tomato ISA

Nine opcode bits index a 512-row control ROM. 91 instructions plus NOP occupy 92 burned rows. The rest stay open as the map grows.

Authority · docs/isa/tomato.v1.csv · download CSV · why it is built this way

01 / ROM

The whole opcode space.

Every cell is one ROM address. Filled cells jump to the burned opcode below. Empty cells are honest spare—ready for the path to 512.

92 burned · 420 open · 512 ROM rows

— Hover or tap a cell Hex address and operation appear here

BurnedOpen · grows toward 512

02 / BURNED

The 91 instructions plus NOP.

Every burn below is a real ROM row from tomato.v1.csv. Spacing stays even so new burns can land without redesigning the sheet.

System

5
  1. 0x00NOPreg_reg

    no operation

    idle / padding

  2. 0xE0FENCEreg_reg

    ordering nop

  3. 0xE1ECALLreg_reg

    trap 0x100

  4. 0xE2EBREAKreg_reg

    halt (debug)

  5. 0xFFHALTreg_reg

    halt

ALU · register

48
  1. 0x01ADDreg_reg

    ADD

    arith

  2. 0x02SUBreg_reg

    SUB

    arith

  3. 0x03ANDreg_reg

    AND

    logic

  4. 0x04ORreg_reg

    OR

    logic

  5. 0x05XORreg_reg

    XOR

    logic

  6. 0x06MOVreg_reg

    MOV

    copy

  7. 0x07CMPreg_reg

    flags = rA - rB

    branches

  8. 0x08MASKADDreg_reg

    rd = rA + (rB & rC)

    compound three-input ALU

  9. 0x09XORANDreg_reg

    rd = (rA ^ rB ^ rC) + (rA & rB & rC)

    compound three-input ALU

  10. 0x0AANDNreg_reg

    rd = rA & ~rB

    masked two-input ALU

  11. 0x0BORNreg_reg

    rd = rA | ~rB

    masked two-input ALU

  12. 0x0CCSELreg_reg

    rd = rC ? rA : rB

    compound three-input ALU

  13. 0x0DANDADDreg_reg

    rd = (rA & rB) + rC

    compound three-input ALU

  14. 0x0EORADDreg_reg

    rd = (rA | rB) + rC

    compound three-input ALU

  15. 0x0FXORADDreg_reg

    rd = (rA ^ rB) + rC

    compound three-input ALU

  16. 0x17ADCreg_reg

    rd = rA + rB + C

    carry / reverse subtract

  17. 0x18SBCreg_reg

    rd = rA - rB + C_in

    carry / reverse subtract

  18. 0x19RSBreg_reg

    rd = rB - rA

    carry / reverse subtract

  19. 0x1AXORBCreg_reg

    rd = rA ^ (rB & rC)

    nested Boolean Dual-LUT

  20. 0x1BXORBOreg_reg

    rd = rA ^ (rB | rC)

    nested Boolean Dual-LUT

  21. 0x1CXORBXreg_reg

    rd = rA ^ (rB ^ rC)

    nested Boolean Dual-LUT

  22. 0x1DANDBOreg_reg

    rd = rA & (rB | rC)

    nested Boolean Dual-LUT

  23. 0x1EANDBXreg_reg

    rd = rA & (rB ^ rC)

    nested Boolean Dual-LUT

  24. 0x1FANDBCreg_reg

    rd = rA & (rB & rC)

    nested Boolean Dual-LUT

  25. 0x25ORBCreg_reg

    rd = rA | (rB & rC)

    nested Boolean Dual-LUT

  26. 0x26ORBOreg_reg

    rd = rA | (rB | rC)

    nested Boolean Dual-LUT

  27. 0x27ORBXreg_reg

    rd = rA | (rB ^ rC)

    nested Boolean Dual-LUT

  28. 0x28NANDANDreg_reg

    rd = ~(rA & (rB & rC))

    nested Boolean Dual-LUT

  29. 0x2ANANDORreg_reg

    rd = ~(rA & (rB | rC))

    nested Boolean Dual-LUT

  30. 0x2BNANDXORreg_reg

    rd = ~(rA & (rB ^ rC))

    nested Boolean Dual-LUT

  31. 0x2CNANDNANDreg_reg

    rd = ~(rA & ~(rB & rC))

    nested Boolean Dual-LUT

  32. 0x2DNANDNORreg_reg

    rd = ~(rA & ~(rB | rC))

    nested Boolean Dual-LUT

  33. 0x2ENANDXNORreg_reg

    rd = ~(rA & ~(rB ^ rC))

    nested Boolean Dual-LUT

  34. 0x2FNORANDreg_reg

    rd = ~(rA | (rB & rC))

    nested Boolean Dual-LUT

  35. 0x32NORORreg_reg

    rd = ~(rA | (rB | rC))

    nested Boolean Dual-LUT

  36. 0x33NORXORreg_reg

    rd = ~(rA | (rB ^ rC))

    nested Boolean Dual-LUT

  37. 0x34NORNANDreg_reg

    rd = ~(rA | ~(rB & rC))

    nested Boolean Dual-LUT

  38. 0x35NORNORreg_reg

    rd = ~(rA | ~(rB | rC))

    nested Boolean Dual-LUT

  39. 0x36NORXNORreg_reg

    rd = ~(rA | ~(rB ^ rC))

    nested Boolean Dual-LUT

  40. 0x37ANDNANDreg_reg

    rd = rA & ~(rB & rC)

    nested Boolean Dual-LUT

  41. 0x38ANDNORreg_reg

    rd = rA & ~(rB | rC)

    nested Boolean Dual-LUT

  42. 0x39ANDXNORreg_reg

    rd = rA & ~(rB ^ rC)

    nested Boolean Dual-LUT

  43. 0x3AORNANDreg_reg

    rd = rA | ~(rB & rC)

    nested Boolean Dual-LUT

  44. 0x3BORNORreg_reg

    rd = rA | ~(rB | rC)

    nested Boolean Dual-LUT

  45. 0x3CORXNORreg_reg

    rd = rA | ~(rB ^ rC)

    nested Boolean Dual-LUT

  46. 0x3DXORNANDreg_reg

    rd = rA ^ ~(rB & rC)

    nested Boolean Dual-LUT

  47. 0x3EXORNORreg_reg

    rd = rA ^ ~(rB | rC)

    nested Boolean Dual-LUT

  48. 0x3FXORXNORreg_reg

    rd = rA ^ ~(rB ^ rC)

    nested Boolean Dual-LUT

Multiply / divide

7
  1. 0x10MULreg_reg

    rd = low(rA*rB)

  2. 0x11MULHreg_reg

    rd = high(rA*rB)

  3. 0x12DIVreg_reg

    rd = rA / rB

  4. 0x13REMreg_reg

    rd = rA % rB

  5. 0x14MULHUreg_reg

    rd = high unsigned

  6. 0x15DIVUreg_reg

    rd = rA / rB unsigned

  7. 0x16REMUreg_reg

    rd = rA % rB unsigned

ALU · immediate

8
  1. 0x20ADDIoff13s

    rd = rA + imm13

    constants

  2. 0x21ANDIimm16z

    rd = rA & imm

  3. 0x22ORIimm16z

    rd = rA | imm

  4. 0x23XORIimm16z

    rd = rA ^ imm

  5. 0x24LUIimm20

    rd = imm20 << 12

    VGA/MMIO base

  6. 0x29RORIreg_reg

    rd = rA ror imm

  7. 0x30ZEROreg_reg

    rd = 0

  8. 0x31ONEreg_reg

    rd = 1

Shift / rotate

4
  1. 0x40LSLreg_reg

    LSL

  2. 0x41LSRreg_reg

    LSR

  3. 0x42ASRreg_reg

    ASR

  4. 0x43RORreg_reg

    ROR

Memory

7
  1. 0x60LWreg_reg

    LW

  2. 0x61LBreg_reg

    LB

  3. 0x62LHreg_reg

    LH

  4. 0x63LBUreg_reg

    LBU

  5. 0x64LHUreg_reg

    LHU

  6. 0x68SWreg_reg

    SW

  7. 0x69SBreg_reg

    SB

Branch

4
  1. 0x80BEQreg_reg

    BEQ

  2. 0x81BNEreg_reg

    BNE

  3. 0x82BLTreg_reg

    BLT

  4. 0x83BGEreg_reg

    BGE

Jump

5
  1. 0xA0JMPreg_reg

    PC = abs

  2. 0xA1JALreg_reg

    link; PC=abs

  3. 0xA2RETreg_reg

    PC = link

  4. 0xA3JRreg_reg

    PC = rB

  5. 0xA4JALRreg_reg

    rd=PC+1; PC=alu

Stack / I/O

4
  1. 0xC0PUSHreg_reg

    SP-=; mem[SP]=rA

  2. 0xC1POPreg_reg

    rd=mem[SP]; SP+=

  3. 0xC8INreg_reg

    rd = kb_data

  4. 0xC9OUTreg_reg

    io_out = rA[7:0]

03 / WORKFLOW

How you use it

  1. Burn an opcode in tomato.v1.csv. Empty rows stay nop—not fake mnemonics.
  2. Assemble with software/assembler.py. Mnemonics come from the CSV.
  3. Add sugar in tomato.v1.pseudo.csv when you want CALL, BEQZ, or LI without growing the ROM.
  4. Map another ISA as rows in profiles/—overlay bits, immediate encoding, LUT pair—not new microcode.

Native form is opcode rd, rA, rB, rC where the ALU computes rd = f(a,b,c) + g(a,b,c) + cin. Rebuild this page after CSV changes: npm run build-isa.

04 / AUTHORITY

Source files

FileWhen you touch it
tomato.v1.csvAdd or rename a burned opcode
tomato.v1.pseudo.csvAssembler macros over existing burns
lut.csvALU primitives · hardware reference
profiles/Foreign ISA maps onto these burns

A profile map is not proof of binary compatibility. Decode, exceptions, and memory behavior still matter. Full argument

From the build

The work behind the words.

Modular microcode control schematic
Control beside the datapath

The modular control design documented in the build journal.

Tetris running in Tomato OS
Software using the machine

Tetris in Tomato OS, written for the custom instruction set.