The cells of Tomato may not seem to undergo reprogramming for each operation. The philosophy: what if computers had the flexibility of an FPGA without the rigidity of programming for every other operation?

I have considered a latched behaviour for the ALU. Each opcode that enters the LUT3s would have an 8-bit latch, plus an MSB enable. If the current operation is ADD, and I do not explicitly run a new operation, the ALU remains a full adder. Assert an instruction, get the result; if the next operations are still ADD, only pass the next operands from the register file.

This latch is a step toward a future version that intrigues me: a dedicated latch for each LUT3, the decoder enabling one or more at a time. FPGA-like behaviour without moving away from the original premise of flexibility in computing.

For this design I will latch only the 16-bit global opcode truth table. Stability for setup and hold. Operational completeness without a truth-table blackout while the cells are still resolving a result.